forked from github/verilator
26 lines
496 B
Systemverilog
26 lines
496 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// bug1364
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module t (/*AUTOARG*/
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// Inputs
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clk, res
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);
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input clk;
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input res;
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typedef struct packed {
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logic [3:0] port_num;
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} info_t;
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info_t myinfo;
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always_comb
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myinfo = '{default: '0,
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default: '1}; // Bad
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endmodule
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