forked from github/verilator
30 lines
988 B
Perl
30 lines
988 B
Perl
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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$Self->{vlt} or $Self->skip("Verilator only test");
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top_filename("t/t_alw_reorder.v");
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compile (
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verilator_flags2 => ["--stats -Or"],
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);
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file_grep ($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0);
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# Here we should see some dly vars since reorder is disabled.
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# (Whereas our twin test, t_alw_reorder, should see no dly vars
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# since it enables the reorder step.)
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file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", qr/dly__t__DOT__v1/i);
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file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.cpp", qr/dly__t__DOT__v2/i);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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