forked from github/verilator
34 lines
661 B
Systemverilog
34 lines
661 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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rc, rg, ri, rp
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);
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parameter P = 15;
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output reg [3:0] rc;
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output reg [3:0] rg;
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output reg [3:0] ri;
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output reg [3:0] rp;
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for (genvar g=0; g < 15; ++g) begin
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// bug1487
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// This isn't a width violation, as genvars are generally 32 bits
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initial begin
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rg = g;
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rp = P;
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rc = 1;
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end
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end
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initial begin
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for (integer i=0; i < 15; ++i) begin
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ri = i;
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end
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end
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endmodule
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