forked from github/verilator
23 lines
470 B
Coq
23 lines
470 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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interface counter_io;
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logic [3:0] value;
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logic reset;
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modport counter_side (input reset, output value);
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modport core_side (output reset, input value);
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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clk,
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counter_io.counter_side c_data
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);
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input clk;
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integer cyc=1;
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endmodule
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