forked from github/verilator
28 lines
632 B
Systemverilog
28 lines
632 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module vlvbound_test
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(
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input logic [15:0] i_a,
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input logic [15:0] i_b,
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output logic [6:0] o_a,
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output logic [6:0] o_b
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);
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function automatic logic [6:0] foo(input logic [15:0] val);
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logic [6:0] ret;
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integer i;
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for (i=0 ; i < 7; i++) begin
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ret[i] = (val[i*2 +: 2] == 2'b00);
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end
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return ret;
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endfunction
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assign o_a = foo(i_a);
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assign o_b = foo(i_b);
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endmodule
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