forked from github/verilator
11 lines
212 B
Systemverilog
11 lines
212 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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//bug1577
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module t;
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always @ c.a c:h;
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endmodule
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