verilator/test_regress/t/t_gen_upscope.out

created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag   = top.t.tag
mod b has scope = top.t.b
mod b has tag   = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag   = top.t.b.gen[0].tag
mod c has scope = top.t.b.gen[1].c
mod c has tag   = top.t.b.gen[1].tag
*-* All Finished *-*
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`created tag with scope = top.t.tag`
Tests: Favor golden files over long regexps. No functional change. 2018-11-03 18:59:04 +00:00			`created tag with scope = top.t.b.gen[0].tag`
			`created tag with scope = top.t.b.gen[1].tag`
			`mod a has scope = top.t`
			`mod a has tag = top.t.tag`
			`mod b has scope = top.t.b`
			`mod b has tag = top.t.tag`
			`mod c has scope = top.t.b.gen[0].c`
			`mod c has tag = top.t.b.gen[0].tag`
			`mod c has scope = top.t.b.gen[1].c`
			`mod c has tag = top.t.b.gen[1].tag`
			`- All Finished -`