forked from github/verilator
15 lines
303 B
Systemverilog
15 lines
303 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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// Illegal with ANSI Verilog 2001 style ports
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module t
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(
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output bad_o_w,
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output bad_o_r);
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wire bad_o_w;
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reg bad_o_r;
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endmodule
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