forked from github/verilator
37 lines
1.1 KiB
Coq
37 lines
1.1 KiB
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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module t (/*AUTOARG*/);
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typedef struct packed {
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logic [3:2] a;
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logic [5:4][3:2] b;
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} ab_t;
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typedef ab_t [7:6] c_t; // array of structs
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typedef struct packed {
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c_t [17:16] d;
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} e_t;
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`define check(got,expec) do if ((got) != (expec)) begin $display("Line%d: Got %b Exp %b\n", `__LINE__, (got), (expec)); $stop; end while(0);
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initial begin
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e_t e;
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if ($bits(ab_t)!=6) $stop;
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if ($bits(c_t)!=12) $stop;
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if ($bits(e_t)!=24) $stop;
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e = 24'b101101010111010110101010;
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`check(e, 24'b101101010111010110101010);
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e.d[17] = 12'b111110011011;
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`check(e, 24'b111110011011010110101010);
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e.d[16][6] = 6'b010101;
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`check(e, 24'b111110011011010110010101);
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e.d[16][6].b[5] = 2'b10;
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`check(e, 24'b111110011011010110011001);
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e.d[16][6].b[5][2] = 1'b1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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