forked from github/verilator
15 lines
301 B
Coq
15 lines
301 B
Coq
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// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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dim1
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);
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reg [1:0] dim1 [1:0];
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output dim1; // Bad, can't output multi-dim
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endmodule
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