forked from github/verilator
22 lines
651 B
Systemverilog
22 lines
651 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2022 by Geza Lore. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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module a #(parameter N) ();
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generate if (N > 1) begin
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// With N == 5, this will first expand N == 2, then expand N == 3,
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// which instantiates N == 2. This requires fixing up topological order
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// in V3Param.
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a #(.N( N/2)) sub_lo();
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a #(.N(N-N/2)) sub_hi();
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end
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endgenerate
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endmodule
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module top();
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a #(.N(5)) root ();
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endmodule
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