forked from github/verilator
56 lines
1.3 KiB
Systemverilog
56 lines
1.3 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2022 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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module sub (
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output logic [31:0] sub_s1up_out[0:0] /* verilator public_flat_rw */,
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input logic sub_clk,
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input logic [31:0] sub_s1up_in[0:0] /* verilator public_flat_rw */
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);
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// Evaluate clock edges
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always @(posedge sub_clk) begin
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sub_s1up_out <= sub_s1up_in;
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end
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endmodule
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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logic [31:0] s1up_in[1];
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logic [31:0] s1up_out[1];
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sub the_sub (
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.sub_s1up_in (s1up_in),
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.sub_s1up_out (s1up_out),
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.sub_clk (clk));
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always_comb s1up_in[0] = cyc;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 10) begin
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if (s1up_out[0] != 9) begin
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$display("%%Error: got %0d instead of 9", s1up_out);
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$stop;
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end
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if (the_sub.sub_s1up_in[0] != 10) begin
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$display("%%Error: the_sub.sub_s1up_in was %0d instead of 10", the_sub.sub_s1up_in[0]);
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$stop;
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end
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$display("final cycle = %0d", cyc);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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