forked from github/verilator
28 lines
537 B
Systemverilog
28 lines
537 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module for Issue#2938
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2021 by Julien Margetts (Originally provided by YanJiun)
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module test (
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input [2:0] a,
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input [3:0] c,
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output reg [7:0] b
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);
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integer i;
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always @ (*)
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begin
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case(a)
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{3'b000}: b = 8'd1;
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{3'b001}:
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for(i=0;i<4;i=i+1) b[i*2+:2] = 2'(c[i]);
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{3'b010}: b = 8'd3;
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{3'b011}: b = 8'd4;
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default : b = 0;
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endcase
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end
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endmodule
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