forked from github/verilator
22 lines
451 B
Systemverilog
22 lines
451 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef class ClsB;
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class ClsA #(parameter PARAM = 12);
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ClsB #(PARAM+1) b;
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endclass
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class ClsB #(parameter PARAM = 12);
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ClsA #(PARAM+1) a;
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endclass
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module t (/*AUTOARG*/);
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ClsA #(.PARAM(15)) c; // Bad param name
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endmodule
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