verilator/test_regress/t/t_flag_debugi9.v

12 lines
259 B
Systemverilog
Raw Normal View History

2019-06-30 21:38:41 +00:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule