forked from github/verilator
19 lines
284 B
Systemverilog
19 lines
284 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Wilson Snyder.
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// Should have been:
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//module t #(
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module t
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(
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FOO=1
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) (
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output bar
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);
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assign bar = FOO;
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endmodule
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