forked from github/verilator
28 lines
529 B
Systemverilog
28 lines
529 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005-2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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endclass
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class Other;
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endclass
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enum { ZERO } e;
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module t (/*AUTOARG*/);
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int i;
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int v;
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Base b;
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Other o;
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initial begin
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i = $cast(v, 1); // 1
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i = $cast(b, b); // 1
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i = $cast(b, o); // 0
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i = $cast(e, 0); // 1
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i = $cast(e, 10); // 0
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end
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endmodule
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