forked from github/verilator
23 lines
494 B
Plaintext
23 lines
494 B
Plaintext
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// $Id:$ -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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// This file is named .vi to test +libext+ flags.
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module t_inst_v2k_sub
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(
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output reg [7:0] osizedreg,
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output wire oonewire /*verilator public*/,
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input [7:0] isizedwire,
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input wire ionewire
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);
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assign oonewire = ionewire;
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always @* begin
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osizedreg = isizedwire;
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end
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endmodule
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