forked from github/verilator
11 lines
211 B
Plaintext
11 lines
211 B
Plaintext
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2010 by Wilson Snyder.
|
||
|
|
|
||
|
|
module xx;
|
||
|
|
|
||
|
|
xx // intentional error
|
||
|
|
|
||
|
|
endmodule
|