forked from github/verilator
37 lines
881 B
Coq
37 lines
881 B
Coq
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2012 by Wilson Snyder.
|
||
|
|
|
||
|
|
//bug591
|
||
|
|
|
||
|
|
module t (/*AUTOARG*/);
|
||
|
|
|
||
|
|
function real ABS (real num);
|
||
|
|
ABS = (num < 0) ? -num : num;
|
||
|
|
endfunction
|
||
|
|
|
||
|
|
function logic range_chk;
|
||
|
|
input real last;
|
||
|
|
input real period;
|
||
|
|
input real cmp;
|
||
|
|
range_chk = 0;
|
||
|
|
if ( last >= 0 ) begin
|
||
|
|
if ( ABS(last - period) > cmp ) begin
|
||
|
|
range_chk = 1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
endfunction
|
||
|
|
|
||
|
|
initial begin
|
||
|
|
if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop;
|
||
|
|
if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop;
|
||
|
|
if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop;
|
||
|
|
if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop;
|
||
|
|
if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop;
|
||
|
|
$write("*-* All Finished *-*\n");
|
||
|
|
$finish;
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|