forked from github/verilator
74 lines
1.4 KiB
Coq
74 lines
1.4 KiB
Coq
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// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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reg [2:0] value;
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reg [31:0] global;
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initial begin
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global = 1;
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value = 2;
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if (add(value) != 3'd3) $stop;
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if (global != 2) $stop;
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if (add(add(3'd1)) != 3'd3) $stop;
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if (global != 4) $stop;
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if (munge4(4'b0010) != 4'b1011) $stop;
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if (global != 5) $stop;
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setit;
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incr(global,global,32'h10);
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if (global != 32'h17) $stop;
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nop(32'h11);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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function [2:0] add;
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input [2:0] from;
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begin
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add = from + 3'd1;
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begin : named
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reg [31:0] flocal;
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flocal = 1;
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global = global + flocal;
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end
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end
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endfunction
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function [3:0] munge4;
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input [3:0] from; // Different from the 'from' signal above
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reg one;
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begin : named
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reg [1:0] flocal;
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// Function calling a function
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one = 1'b1;
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munge4 = {one, add(from[2:0])};
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end
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endfunction
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task setit;
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reg [31:0] temp;
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begin
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temp = global + 32'h1;
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global = temp + 32'h1;
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end
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endtask
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task incr;
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output [31:0] z;
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input [31:0] a;
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input [31:0] inc;
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z = a + inc;
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endtask
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task nop;
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input [31:0] a;
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begin
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end
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endtask
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endmodule
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