verilator/test_regress/t/t_unopt_converge_print_bad.out

-V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] x)
%Error: t/t_unopt_converge.v:7: Settle region did not converge.
Aborting...
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`-V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] x)`
			`%Error: t/t_unopt_converge.v:7: Settle region did not converge.`
Improve error messages on DIDNOTSETTLE, bug1556. 2019-11-07 00:47:34 +00:00			`Aborting...`