forked from github/verilator
16 lines
311 B
Systemverilog
16 lines
311 B
Systemverilog
|
// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2020 by Julien Margetts.
|
||
|
|
|
||
|
|
module t (/*AUTOARG*/ a, b, o);
|
||
|
|
input a;
|
||
|
|
input b;
|
||
|
|
output reg o;
|
||
|
|
|
||
|
|
always @(a or b)
|
||
|
|
if (a)
|
||
|
|
o <= b;
|
||
|
|
|
||
|
|
endmodule
|