forked from github/verilator
13 lines
296 B
Systemverilog
13 lines
296 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Rafal Kapuscik
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// SPDX-License-Identifier: CC0-1.0
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//
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class Cls;
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task t;
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super.i = 1; // Bad - no extends
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endtask
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endclass
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