forked from github/verilator
29 lines
483 B
Coq
29 lines
483 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2010 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg sync_blk;
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reg sync_nblk;
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reg combo_blk;
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reg combo_nblk;
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always @(posedge clk) begin
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sync_blk = 1'b1;
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sync_nblk <= 1'b1;
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end
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always @* begin
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combo_blk = 1'b1;
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combo_nblk <= 1'b1;
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end
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endmodule
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