forked from github/verilator
24 lines
440 B
Systemverilog
24 lines
440 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class ClsDup;
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int vardup;
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int vardup;
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task memdup;
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endtask
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task memdup;
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endtask
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function void funcdup;
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endfunction
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function void funcdup;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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endmodule
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