2010-01-21 11:11:30 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2020-03-21 15:24:24 +00:00
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2010-01-21 11:11:30 +00:00
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`verilator_config
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2020-03-21 15:24:24 +00:00
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lint_off -rule DEPRECATED -file "t/t_vlt_warn.vlt" -lines 14
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2020-01-03 16:27:51 +00:00
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lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v"
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2020-03-21 15:24:24 +00:00
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lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 19
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2020-01-12 09:03:17 +00:00
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lint_off -rule DECLFILENAME -file "*/t_vlt_warn.v"
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2010-12-30 00:14:49 +00:00
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// Test wildcard filenames
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2020-03-21 15:24:24 +00:00
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lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 20-20
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2010-12-30 11:58:02 +00:00
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// Test global disables
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2020-03-21 15:24:24 +00:00
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lint_off -file "*/t_vlt_warn.v" -lines 21-21
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2020-01-12 09:03:17 +00:00
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// Test match
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lint_off -rule UNUSED -file "*/t_vlt_warn.v" -match "Signal is not used: 'width_warn*'"
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2010-01-21 11:11:30 +00:00
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coverage_off -file "t/t_vlt_warn.v"
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// Test --flag is also accepted
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tracing_off --file "t/t_vlt_warn.v"
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