forked from github/verilator
17 lines
358 B
Systemverilog
17 lines
358 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Yossi Nivin.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer count;
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assign count = $countbits(32'h123456, '0, '1, 'x, 'z);
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endmodule
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