forked from github/verilator
23 lines
517 B
Systemverilog
23 lines
517 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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reg arr [15:0];
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reg mat [3:0] [3:0];
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initial begin
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for (int i = 0; i < 16; i++) begin
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arr[i] = ^i;
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mat[i/4][i%4] = ^i;
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end
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$display("%%p=%p", arr);
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$display("%%p=%p", mat);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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