forked from github/verilator
57 lines
1.3 KiB
Systemverilog
57 lines
1.3 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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typedef struct {
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int a;
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int b;
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byte c;
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} sabcu_t;
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typedef struct packed {
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int a;
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int b;
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byte c;
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} sabcp_t;
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sabcu_t abcu;
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sabcp_t abcp;
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initial begin
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abcp = '{1, 2, 3};
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abcu = '{1, 2, 3};
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if (abcp.a !== 1) $stop;
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if (abcp.b !== 2) $stop;
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if (abcp.c !== 3) $stop;
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if (abcu.a !== 1) $stop;
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if (abcu.b !== 2) $stop;
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if (abcu.c !== 3) $stop;
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abcp = '{default:4, int:5};
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abcu = '{default:4, int:5};
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if (abcp.a !== 5) $stop;
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if (abcp.b !== 5) $stop;
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if (abcp.c !== 4) $stop;
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if (abcu.a !== 5) $stop;
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if (abcu.b !== 5) $stop;
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if (abcu.c !== 4) $stop;
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abcp = '{int:6, byte:7, int:8};
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abcu = '{int:6, byte:7, int:8};
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if (abcp.a !== 8) $stop;
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if (abcp.b !== 8) $stop;
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if (abcp.c !== 7) $stop;
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if (abcu.a !== 8) $stop;
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if (abcu.b !== 8) $stop;
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if (abcu.c !== 7) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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