forked from github/verilator
22 lines
483 B
Systemverilog
22 lines
483 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface class Icls1;
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pure virtual function int icf1;
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pure virtual function int icf2;
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endclass
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class Cls implements Icls1;
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virtual function int icf1;
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return 1;
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endfunction
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// Bad missing icf2
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endclass
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module t (/*AUTOARG*/);
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Cls c;
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endmodule
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