forked from github/verilator
9 lines
414 B
Plaintext
9 lines
414 B
Plaintext
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@@ -2,7 +2,7 @@
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NETLIST 0x <e> {a0aa} $root [1ps/1ps]
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1: MODULE 0x <e> {d19ai} t L2 [1ps]
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1:2: PORT 0x <e> {d21ae} clk
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+ 1:2: VAR 0x <e> {d23ak} @dt=0@ clkmod INPUT PORT
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1:2:1: BASICDTYPE 0x <e> {d23ak} @dt=this@(nw0) LOGIC_IMPLICIT kwd=LOGIC_IMPLICIT
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3: TYPETABLE 0x <e> {a0aa}
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logic -> BASICDTYPE 0x <e> {d55ap} @dt=this@(G/nw1) logic [GENERIC] kwd=logic
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