forked from github/verilator
3 lines
158 B
Plaintext
3 lines
158 B
Plaintext
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%Error-WIDTH: t/t_flag_werror.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
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%Error: Exiting due to
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