forked from github/verilator
28 lines
633 B
Systemverilog
28 lines
633 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk, unk, nonconst, mi
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);
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input clk;
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input unk;
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input nonconst;
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input [45:40] mi;
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reg [3:0] sel2;
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reg [1<<29 : 0] hugerange;
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always @ (posedge clk) begin
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sel2 = mi[44 +: -1];
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sel2 = mi[44 +: 1<<29];
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sel2 = mi[44 +: nonconst];
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sel2 = mi[nonconst];
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sel2 = mi[nonconst : nonconst];
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sel2 = mi[1<<29 : 0];
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end
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endmodule
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