forked from github/verilator
16 lines
446 B
Systemverilog
16 lines
446 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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always @(posedge clk) begin
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$c("const CData xthis = this->clk;");
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$c("const CData thisx = xthis;");
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$c("const CData xthisx = thisx;");
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$c("this->clk = xthisx;");
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end
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endmodule
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