forked from github/verilator
31 lines
942 B
Systemverilog
31 lines
942 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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initial begin
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int q[$];
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int qe[$]; // Empty
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int qv[$]; // Value returns
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int qi[$]; // Index returns
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q = '{2, 2, 4, 1, 3};
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qv = q.unique with (1); // Bad no with allowed
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q.reverse(1); // Bad no args allowed
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q.shuffle(1); // Bad no args allowed
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qv = q.find; // Bad missing with
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qv = q.find_first; // Bad missing with
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qv = q.find_last; // Bad missing with
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qi = q.find_index; // Bad missing with
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qi = q.find_first_index; // Bad missing with
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qi = q.find_last_index; // Bad missing with
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qi = q.size with (1); // with not allowed
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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