forked from github/verilator
41 lines
769 B
Coq
41 lines
769 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic foo; initial foo = 0;
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// dut #(.W(4)) udut(.*);
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dut #(.W(4)) udut(.clk(clk),
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.foo(foo)); // Should be a non-internal error, as assigning logic to logic array
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endmodule
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module dut
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#(parameter W = 1)
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(input logic clk,
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input logic foo[W-1:0]);
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genvar i;
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generate
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for (i = 0; i < W; i++) begin
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suba ua(.clk(clk), .foo(foo[i]));
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end
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endgenerate
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endmodule
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module suba
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(input logic clk,
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input logic foo);
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always @(posedge clk)
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$display("foo=%b", foo);
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endmodule
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