forked from github/verilator
30 lines
556 B
Systemverilog
30 lines
556 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2022 by Wilson Snyder.
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module flop (
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output reg q,
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input wire d,
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input wire clk
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);
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// verilator hier_block
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always_ff @(posedge clk) begin
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q <= d;
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end
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endmodule
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module t (
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output wire q,
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input wire d,
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input wire clk
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);
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// This intentionally uses pin number ordering
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flop u_flop(q, d, clk);
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endmodule
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