forked from github/verilator
9 lines
236 B
Plaintext
9 lines
236 B
Plaintext
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2020 by Yutetsu TAKATSUKASA
|
||
|
|
|
||
|
|
`verilator_config
|
||
|
|
hier_block -module "sub?"
|
||
|
|
hier_block -module "delay"
|