forked from github/verilator
24 lines
596 B
Coq
24 lines
596 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t;
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integer varfirst;
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sub varfirst (); // Error: Cell hits var
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task varfirst; begin end endtask // Error: Task hits var
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sub cellfirst ();
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integer cellfirst; // Error: Var hits cell
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task cellfirst; begin end endtask // Error: Task hits cell
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task taskfirst; begin end endtask
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integer taskfirst; // Error: Var hits task
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sub taskfirst (); // Error: Cell hits task
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endmodule
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module sub;
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endmodule
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