verilator/test_regress/t/t_preproc_cmtend_bad.v

8 lines
172 B
Systemverilog
Raw Normal View History

2019-10-19 01:30:34 +00:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
/*Blah
blah