verilator/test_regress/t/t_pp_pragma_bad.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.

`pragma

`resetall  // Ok
module t;
`resetall  // Bad
endmodule
`resetall  // Ok
With -Wpedentic, warn about bad `pragma 2019-12-14 15:13:38 +00:00			`// DESCRIPTION: Verilator: Verilog Test module`
			`//`
			`// This file ONLY is placed into the Public Domain, for any use,`
			`// without warranty, 2019 by Wilson Snyder.`

			`pragma
Add error when `resetall inside module 2019-12-15 03:04:58 +00:00
			`resetall // Ok
			`module t;`
			`resetall // Bad
			`endmodule`
			`resetall // Ok