forked from github/verilator
46 lines
795 B
Systemverilog
46 lines
795 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Wilson Snyder.
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// Very simple test for interface pathclearing
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interface ifc;
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logic [3:0] value;
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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ifc itop();
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sub c1 (.isub(itop),
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.i_value(4'h4));
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==20) begin
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if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison
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if (itop.value != 4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub
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(
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ifc isub,
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input logic [3:0] i_value
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);
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always @* begin
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isub.value = i_value;
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end
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endmodule : sub
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