verilator/test_regress/t/t_flag_wpedantic_bad.v

9 lines
209 B
Systemverilog
Raw Normal View History

2019-11-16 16:59:21 +00:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
module t (/*AUTOARG*/);
reg global;
endmodule