forked from github/verilator
11 lines
333 B
Systemverilog
11 lines
333 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2017 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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module t;
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t_flag_relinc_sub sub ();
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endmodule
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