forked from github/verilator
12 lines
247 B
Systemverilog
12 lines
247 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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module t;
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initial begin
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// verilator lint_off FUTURE1
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$write("*-* All Finished *-*\n");
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$finish;
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// verilator FUTURE2
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// verilator FUTURE2 blah blah
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end
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endmodule
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