forked from github/verilator
20 lines
341 B
Coq
20 lines
341 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Wilson Snyder.
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// issue 1991
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module t
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#(
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parameter[96:0] P = 97'h12344321_12344321_12344327
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)
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(
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input [P&7 - 1:0] in,
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output [P&7 - 1:0] out
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);
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wire out = in;
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endmodule
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