forked from github/verilator
74 lines
1.6 KiB
Coq
74 lines
1.6 KiB
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [67:0] q;
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reg signed [67:0] qs;
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initial begin
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q = 68'he_12345678_9abcdef0 ** 68'h3;
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if (q != 68'hcee3cb96ce96cf000) $stop;
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//
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q = 68'he_12345678_9abcdef0 ** 68'h5_6789abcd_ef012345;
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if (q != 68'h0) $stop;
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//
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qs = 68'she_12345678_9abcdef0 ** 68'sh3;
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if (qs != 68'shcee3cb96ce96cf000) $stop;
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//
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qs = 68'she_12345678_9abcdef0 ** 68'sh5_6789abcd_ef012345;
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if (qs != 68'h0) $stop;
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end
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reg [67:0] left;
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reg [67:0] right;
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wire [67:0] outu = left ** right;
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wire signed [67:0] outs = $signed(left) ** $signed(right);
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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`ifdef TEST_VERBOSE
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$write("%d %x %x %x %x\n", cyc, left, right, outu, outs);
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`endif
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if (cyc==1) begin
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left <= 68'h1;
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right <= '0;
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end
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if (cyc==2) begin
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if (outu != 68'h1) $stop;
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if (outs != 68'h1) $stop;
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end
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if (cyc==3) begin
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left <= 68'he_12345678_9abcdef0;
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right <= 68'h3;
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end
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if (cyc==4) begin
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if (outu != 68'hcee3cb96ce96cf000) $stop;
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if (outs != 68'hcee3cb96ce96cf000) $stop;
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end
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if (cyc==5) begin
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left <= 68'he_12345678_9abcdef0;
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right <= 68'h5_6789abcd_ef012345;
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end
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if (cyc==6) begin
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if (outu != 68'h0) $stop;
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if (outs != 68'h0) $stop;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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