forked from github/verilator
18 lines
398 B
Systemverilog
18 lines
398 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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// ======================================================================
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module sub
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#(parameter type TYPE_t = logic)
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(
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input TYPE_t in,
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output TYPE_t out
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);
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// Some simple logic
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always_comb out = ~ in;
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endmodule
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