forked from github/verilator
13 lines
323 B
Systemverilog
13 lines
323 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog example module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Wilson Snyder.
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// See also the EXAMPLE section in the verilator manpage/document.
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module top;
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initial begin
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$display("Hello World!");
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$finish;
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end
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endmodule
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